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An interrupt is an event that halts normal processing to handle a special situation. After the interrupt has been dealt with, normal processing resumes.
The DCPU-16 has an interrupt system that encompasses two classes of interrupts: processor-controlled interrupts and peripheral-controlled interrupts.
 Processor-controlled interrupts
The first kind of interrupt is a processor-controlled interrupt. This interrupt may be initiated from a peripheral or from the
INT instruction. Regardless of what initiates the interrupt, it causes the DCPU to either:
- queue the interrupt for later processing (if interrupt queueing is enabled - see below), or
- immediately pause the current task, process the interrupt, and return to the interrupted task (if queueing is disabled).
Whenever such an interrupt is processed, an interrupt service routine (ISR) referenced by the
IA register is entered. When finished, such an ISR must restore the register states to their previous values and return to the interrupted process (using the
RFI instruction). Further interrupts received while processing the ISR are queued until the ISR returns and one instruction from the interrupted task is executed.
 Peripheral-controlled interrupts
The second kind of interrupt is a peripheral-controlled interrupt. Unlike the processor-controlled interrupt, no ISR is executed, and the processor must explicitly hand over control to the peripheral using the
HWI instruction before such an interrupt can take place. A further difference is that the peripheral is granted full, read-and-write access to all of the DCPU's registers and all of the RAM. Finally, the amount of time consumed by such an interrupt is determined by the peripheral itself. When the peripheral is done, the DCPU resumes processing after the triggering
HWI instruction (provided that the
PC has not been modified).
 Returning from an interrupt
- Main article: RFI
RFI instruction should be used to return from an interrupt.
IAS myISR ; interrupts will be handled by myISR (Interrupt Service Routine), below SET a, 1 INT a ADD a, 2 :end SET pc, end :myISR SET b, 1 ADD b, a RFI a ; continues execution at ADD a, 2
 Interrupt queueing
When it is important not to interrupt the current task, but also important to handle all incoming interrupts eventually, interrupt queueing may be enabled. This captures and stores interrupts until queueing is disabled. When queueing is disabled, each interrupt is read from the queue in FIFO (first-in, first-out) order, triggered, and removed from the queue until no interrupts remain. As usual, one instruction from the interrupted task is allowed to execute between interrupts.
Interrupt queueing is enabled implicitly by any interrupt that jumps into the ISR referenced by
IA. In addition, the operator may explicitly turn on interrupt queueing by passing a nonzero argument to the
Disabling queueing is similarly implicitly accomplished when the
RFI instruction is executed at the end of an ISR, or explicitly by passing a zero argument to the same
IAQ instruction mentioned above.
The maximum length of the queue is 256 interrupts. Attempting to queue more than 256 interrupts will cause the DCPU to catch fire. It is therefore wise to enable queueing as little as possible, for small segments of code only. Alternatively, the operator may disable interrupts altogether (see below).
Queueing is disabled by default.
 Disabling interrupts
Interrupts may be disabled by setting the
IA register to zero (with
IAS). This has the additional effect of dropping all queued interrupts, which may be used to prevent the DCPU from catching fire. To enable interrupts again, use
IAS with a non-zero argument; this should be the address of the ISR.
Interrupts are disabled by default.
- DCPU-16 specification v1.7 (Copyright 2012 Mojang)
 See also
- NerdKits - Interrupts: Interfacing a Microcontroller with a PS/2 Keyboard A real-world example of using interrupts with AVR microcontrollers. The DCPU can also have timer interrupts by interfacing with the Generic Clock.